Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its stored data values for some extended period without the application of power. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones and removable memory modules, and the uses for non-volatile memory continue to expand.
Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Storing data in a flash memory cell can be accomplished by changing the threshold voltage (Vt) of the cell, through programming (e.g., “writing”) a charge storage node, such as a charge storage layer or a floating gate or trapping layers or other physical phenomena, for example. By defining two or more ranges of threshold voltages to correspond to individual data values, one or more bits of information may be stored on each cell. Memory cells storing one bit of data by utilizing two threshold voltage ranges are typically referred to as Single Level Cell (SLC) memory cells. Memory cells storing more than one bit of data per cell by utilizing more than two possible threshold voltage ranges are typically referred to as Multilevel Cell (MLC) memory cells.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash wherein the designation is derived from the logic used to read the devices. In NOR flash architecture, a column of memory cells are coupled in parallel with each memory cell coupled to a data line, often referred to as a bit line. In NAND flash architecture, a column (e.g., NAND string) of memory cells are coupled in series with only the first memory cell of each column coupled to a bit line.
Typically in both NOR and NAND configurations, memory cells are logically arranged into arrays of rows and columns. The control gates of memory cells of a given row are coupled by a common access line, which is often referred to as a word line. Programming of flash memory cells is accomplished by applying a programming voltage to selected word lines of the memory array in order to shift the threshold voltages of memory cells selected for programming. Because the memory cells of a given row are coupled to a common word line, each memory cell is therefore subjected to the programming voltage applied to the word line. During a typical programming operation, an initial programming voltage is applied to memory cells which are to undergo a programming operation. Following the initial programming attempt, a verify operation is performed in order to determine if the memory cells have reached their intended programmed levels. If so, the programming operation is complete. If one or more cells have not achieved their intended programmed levels then additional programming operations utilizing increasing programming voltages are repeated, each followed by verify operations, until the memory cells have all reached their intended programmed levels. This process is repeated during each programming operation performed on the memory device.
As memory devices age (e.g., through repeated program/erase cycles) the memory cells can change operating characteristics, such as how they respond to programming and/or erase operations performed on them. Typical programming/erase processes can result in programming operations performed at levels which are unlikely to result in, or substantially contribute to, a successful programming operation. Thus, programming efficiency can be reduced due to the application of programming pulses which are unlikely to significantly affect the programming of selected memory cells during a programming operation. In addition, performing programming operations on memory cells can also affect the programming of other nearby memory cells in the memory device. This phenomenon is typically referred to by those skilled in the art as program disturb effects. Thus, it is desirable to reduce the number of programming operations performed on a memory device.
For the reasons stated above, and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing programming schemes for flash memory devices.